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| ESS Technology, Inc. DESCRIPTION The ES1988 AllegroTM PCI audio-modem accelerator combines advanced audio and modem functionality in a highly integrated PCI solution. Utilizing one PCI load, the ES1988 provides a twochip audio-modem solution with digital interface capability to an AC`97 codec in the dock (a.k.a. digital docking). The ES1988 is designed to provide a low-cost, high-performance solution for notebook PC applications. The high-bandwidth PCI bus and an integrated high-fidelity codec are utilized to deliver advanced PC audio features, such as DirectSoundTM acceleration and HRTF 3D positional audio. The ES1988 implements multistream DirectSound and DirectSound3D acceleration with digital mixing, sample rate conversion, and HRTF 3D filtering for two-speaker 3D positional audio. The programmable audio signal processor provides support for multiple audio streams. With its built-in DSP core, the ES1988 uses its dedicated direct memory access (DMA) engine to handle complex signal processing tasks with a bus-mastering PCI interface. The support functions ensure efficient transfer of audio data streams to and from system memory buffers, providing a system solution with maximum performance and minimal host CPU loading. The architecture enables implementation of communications over the Internet from multiple sources. The ES1988 maintains full DOS legacy audio compatibility over the standard PCI 2.1 and PCI 2.2 bus. Full DOS game compatibility is ensured through either PC/PCI, distributed DMA (DDMA), or transparent DMA (TDMA). The ES1988 includes an HSP modem interface via its secondary AC-Link connecting with the ES2828 MC`97 codec. The MC`97 is used as the analog front end for the modem and DAA control. The V.90 modem runs on the host while the ES1988 serves as the bidirectional buffer for data transmission and reception. The modem functions include the standard AT command set, V.42bis and Group 3 fax. The ES1988 provides a high-quality docking solution through proven AC-link-based digital docking. This is accomplished by using only a five-wire digital connection. The secondary AC`97 link (extension 2.1 compliant) of the ES1988 interfaces to a secondary AC`97 codec in the dock to provide high-quality audio in the dock. The ES1988, which operates at 3.3V digitally and 5.0V in analog, is compliant with the Advanced Power Management (APM) 1.2, Advanced Configuration and Power Interface (ACPI) 1.0, and PCI Power Management Interface (PPMI) 1.0. The ES1988 supports D0, D1, D2, and D3 (hot and cold) power-saving modes for power efficiency when the audio system is both active and idle. CLKRUN# support is also available. The ES1988 is available in an industry-standard 100-pin lowprofile quad flat pack (LQFP) package. ES1988 AllegroTM PCI Audio-Modem Accelerator Product Brief AUDIO FEATURES * * * * * * * * * * * * High-performance single-chip PCI audio acceleration Integrated high-fidelity AC`97 codec Multistream DirectSound and DirectSound 3D acceleration Sensaura(R) CRL positional 3D High-quality sample rate conversion and digital mixing Direct music support Realtime effects processing S/PDIF output for PCM or AC-3 content Full legacy DOS game support, using TDMA, PC/PCI, or DDMA hardware implementation methods Supports one additional PCI bus master devices HSP modem interface via MC`97 link Digital docking via secondary AC-Link MODEM FEATURES * Data mode capabilities: --- --- --- --- --- --- --- --- V.90 56 kbps V.34 33.6 kbps and fallbacks Standard AT command set V.42 (LAPM) and MNP error correction V.42bis/MNP 5 data compression 3.3V power supply with 5V-tolerant inputs ITU-T V.17, V.21 ch2, V.27ter, V.29 Group 3 (TIA/EIA 578 Class 1 and Class 2) * Fax mode capabilities: * Supports wake-on-ring from D3hot and D3cold states POWER MANAGEMENT * * * * Compliance with APM 1.2, ACPI 1.0, and PPMI 1.1 Compliance with Intel's Mobile Power Guidelines `99 3.3V digital operation with 5V-tolerant inputs 5.0V analog operation COMPATIBILITY * Supports PC DOS games and applications for Sound BlasterTM and SoundBlaster ProTM * Meets PC99 /PC2001and WHQL specifications * Compliant with Intel's audio-modem riser card and mini-PCI specifications ESS Technology, Inc. SAM0368-030601 1 ES1988 PRODUCT BRIEF ES1988 PINOUT Figure 1 shows the ES1988 Allegro pinout diagram. AFILT2 CAP1 CAP2 LINE_OUT_L LINE_OUT_R MONO_OUT AVSS2 AVDD2 GPIO1/RXD GPIO2/TXD RST# INT# PCICLK GND VCC GNT# REQ# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AFILT1 VREF AVSS1 AVDD1 LINE_IN_R LINE_IN_L MIC CD_R CD_GND CD_L PHONE PC_BEEP PCGNT#/GT0#/GS0/GPIO12 SDO2/GPIO11/VAUXD SCLK2/GPIO10 SDFS2/GPIO9 SRESET2#/GPIO3 OSCO OSCI SDI2/GPIO8 VAUX PME#/SPDIFO/ PCGNT#/VOLDN# MC97_DI/PCREQ#/VOLUP#/GPIO7 I 2S D A T A / R 0 # / G P I O 6 I 2S L R / G T 0 # / G S O / G P I O 5 75 74 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 ES1988S 100-Pin LQFP 39 38 37 36 35 34 33 32 31 30 29 28 27 26 I2SCLK/SIRQ#/GPIO4 GD7/GPIO15 GD6/GPIO14 GD5/GPIO13 GD4 GD3/ECLK/VOLDN# GD2/EDIN/VOLUP# GD1/EDOUT GD0 VCC GND CLKRUN#/ECS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 C/BE0# AD8 AD9 AD10 AD11 2 SAM0368-030601 C/BE3# PCREQ#/SPDIFO/R0#/IDSEL GND AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 VCC C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PAR C/BE1# GND AD15 AD14 AD13 AD12 Figure 1 ES1988 Allegro Pinout Diagram ESS Technology, Inc. ES1988 PRODUCT BRIEF PIN DESCRIPTION Table 1 lists the ES1988 pin descriptions . Table 1 Names C/BE[3:0]# ES1988 Pin Descriptions Pin Numbers 1, 13, 20, 30 I/O I/O Descriptions PCI command/byte enable. During address phase of a transaction, these pins define the bus command. During data phase, these pins define the byte enable. ID select. When pin 2 is configured as a multifunction pin (see pin 2 note), IDSEL is selected internally to AD24. PCI bus request 0 input from external PCI master device. RO# is enabled by setting the PCIx2 arbiter bit PCI 58h [0] = 1. Select RO# from pin 2 by setting PCI 58h [10] = 1, and pin 2 must be configured as a multifunction pin. Either pin 2 or pin 52 may be used for R0#. S/PDIF output. Enable SPDIFO by setting PCI 53h [0] = 1. Select SPDIFO from pin 2 by setting PCI 58h [1] = 1, and pin 2 must be configured as a multifunction pin. Either pin 2 or pin 54 may be used for SPDIFO. PC/PCI request output. Enable PCREQ# by setting PCI 50h [10:8] = 010. Pin 53 is used as PCREQ# when configured as an audio-only device. PCREQ# can only be used from pin 2 when the ES1988 is configured as a multifunction device (see pin 60 note). Pin 2 must be configured as a multifunction pin. Digital ground. Address and data lines from the PCI bus. IDSEL I R0# I SPDIFO 2 O PCREQ# O GND AD[31:0] 3, 21, 40, 89 4:11, 22:29, 31:38, 93:100 12, 41, 90 14 15 16 17 18 19 I I/O VCC FRAME# IRDY# TRDY# DEVSEL# STOP# PAR CLKRUN# I I/O I/O I/O I/O I/O I/O I/O Digital supply voltage, 3.3V. Cycle frame. Initiator ready. Target ready. Device select. Stop transaction. Parity. Input/output for PCI Clock status and an output to start or accelerate clock function by enabling PCI 52h [11] = 1. Chip select output to EEPROM chip select input. ECS is active after power-on reset and goes inactive automatically after EEPROM cycle is complete. Game port data input/output. Game port data input/output. Data output to EEPROM data input. EDOUT goes active after power-on reset and goes inactive automatically after EEPROM cycle is complete. Game port data input/output. Data input from EEPROM data output. EDIN goes active after power-on reset and goes inactive automatically after EEPROM cycle is complete. Hardware volume control (volume up). Used in combination with pin 45 (VOLDN#). Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 44:45 are selected for hardware volume control by setting PCI 52h [5] = 1. Pins 53:54 may also be used for hardware volume control. 39 ECS O GD[0] GD[1] EDOUT 42 I/O I/O 43 O GD[2] EDIN 44 VOLUP# I/O I I ESS Technology, Inc. SAM0368-030601 3 ES1988 PRODUCT BRIEF Table 1 Names GD[3] ECLK ES1988 Pin Descriptions (Continued) Pin Numbers I/O I/O O 45 Game port data input/output. Clock output to EEPROM clock input. ECLK goes active after power-on reset and goes inactive automatically after EEPROM cycle is complete. Hardware volume control (volume down). Used in combination with pin 44 (VOLUP#). Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 44:45 are selected for hardware volume control by setting PCI 52h [5] = 1. Pins 53:54 may also be used for hardware volume control. Game port data input. Game port data input. General-purpose input/output. I2S serial clock input. I2S input is enabled by setting Allegro_Base+37h [15] = 1. Serial interrupt request. Optional PC/PCI system implementation. Serial IRQ is enabled by setting PCI 40h [14] = 1. General-purpose input/output. I2S frame sync input. I2S input is enabled by setting Allegro_Base+37h [15] = 1. Grant to PCI master. GTO# is enabled by setting PCIx2 arbiter bits PCI 58h [0] = 1 and PCI 58h [11] = 1. Select GT0#/GSO from pin 51 by enabling PCI 58h [10] = 0. Pin 63 may also be used as GT0#/GSO. Grant select 0 output to control external quick switch to grant PCI master phase. GSO is enabled by setting PCIx2 arbiter bit PCI 58h [0] = 1 and PCI 58h [11] = 0. Select GS0/GT0# from pin 51 by enabling PCI 58h [10] = 0. Pin 63 may also be used as GT0#/GSO. General-purpose input/output. I2S data input. I2S input is enabled by setting Allegro_Base+37h [15] = 1. PCI bus request 0 input from external PCI master device. RO# is enabled by setting the PCIx2 arbiter bit PCI 58h [0] = 1. Select R0# from pin 52 by enabling PCI 58h [10] = 0. Either pin 2 or pin 52 may be used for R0#. General-purpose input/output. Modem codec data input. Enabled by setting Allegro_Base+38h [3] = 1. PC/PCI request output. Enable PCREQ# by setting PCI 50h [10:8] = 010. Pin 53 is used as PCREQ# when configured as an audio-only device. PCREQ# can only be used from pin 2 when configured as a multifunction device (see pin 60 note). Hardware volume control (volume up). Used in combination with pin 54 (VOLDN#). Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 53:54 are selected for hardware volume control by setting PCI 52h [5] = 0. Pins 44:45 may also be used for hardware volume control. General-purpose input/output. PME# output to wake the system. PME is enabled by setting the PME_EN bit (PCI C5h [0] = 1). S/PDIF output. Enable SPDIFO by setting PCI 53h [0] = 1. Select SPDIFO from pin 54 by setting PCI 58h [1] = 0. Either pin 2 or pin 54 may be used for SPDIFO. PC/PCI grant input. Enable PC/PCI by setting PCI 50h [10:8] = 010. Select PCGNT# from pin 54 by setting Allegro_Base+58h [6] = 1. Either pin 54 or pin 63 may be used for PCGNT#. Hardware volume control (volume down). Used in combination with pin 53 (VOLUP#). Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 53:54 are selected for hardware volume control by setting PCI 52h [5] = 0. Pins 44:45 may also be used for hardware volume control. 3.3V VAUX voltage supply input. If VAUX is not supported, then VAUX (pin 55) should be connected to VCC and VAUXD (pin 62) should be pulled down. Descriptions VOLDN# I GD[4] GD[5:7] 46 47:49 I I I/O I GPIO[13:15] I2SCLK SIRQ# 50 I/O GPIO4 I2SLR GTO# I/O I O 51 GSO O GPIO5 I2SDATA R0# 52 I/O I I GPIO6 MC_97DI PCREQ# I/O I O 53 VOLUP# I GPIO7 PME# SPDIFO I/O O O PCGNT# 54 I VOLDN# I VAUX 55 I 4 SAM0368-030601 ESS Technology, Inc. ES1988 PRODUCT BRIEF Table 1 Names SDI2 ES1988 Pin Descriptions (Continued) Pin Numbers I/O I 56 Descriptions External AC-link serial data input. Select secondary codec by enabling Allegro_Base+38h [5] = 1. General-purpose input/output. 49.152-MHz crystal input. 49.152-MHz crystal output. Reset output for AC-Link interface. Select secondary codec by enabling Allegro_Base+38h [5] = 1. General-purpose input/output. Serial data frame sync output for AC-Link interface. Select secondary codec by enabling Allegro_Base+38h [5] = 1. General-purpose input/output. If a pull-down resistor is used on this pin, the ES1988 is configured as a multifunction device (audio-modem). Otherwise, the ES1988 is configured as a single function audio-only device. O 61 I/O O Serial clock for AC-link interface. Select secondary codec by enabling Allegro_Base+38h [5] = 1. General-purpose input/output. External AC-link serial data output. Select secondary codec by enabling Allegro_Base+38h [5] = 1. General-purpose input/output. VAUX detect. During the reset period, the V AUXD pin is driven high to indicate ACPI support in the D3cold state, and is driven low to indicate ACPI is not supported in the D3cold state. If V AUX is not supported, then V AUX (pin 55) should be connected to VCC and V AUXD (pin 62) should be pulled down. PC/PCI grant input. Enable PC/PCI by setting PCI 50h [10:8] = 010. Select PCGNT# from pin 63 by setting Allegro_Base+58h [6] = 0. Either pin 54 or pin 63 may be used for PCGNT#. Grant to PCI master. GTO# is enabled by setting PCIx2 arbiter bits PCI 58h [0] = 1 and PCI 58h [11] = 1. Select GT0#/GSO from pin 63 by enabling PCI 58h [10] = 1. Pin 51 may also be used as GT0#/GSO. Grant select 0 output to control external quick switch to grant PCI master phase. GSO is enabled by setting PCIx2 arbiter bit PCI 58h [0] = 1 and PCI 58h [11] = 0. Select GS0/GT0# from pin 63 by enabling PCI 58h [10] = 1. Pin 51 may also be used as GT0#/GSO. General-purpose input/output. PC Speaker input. Mono input. CD-audio left channel input. CD-audio ground input. CD-audio right channel input. Microphone input. Line left channel input. Line right channel input. Analog supply voltage, 5V. Analog ground. Reference voltage. GPIO8 OSCI OSCO SRESET2# 59 GPIO3 SDFS2 57 58 I/O I O O I/O O GPIO9 (note) 60 I/O SCLK2 GPIO10 SDO2 GPIO11 VAUXD 62 I/O I PCGNT# I GT0# 63 GS0 O O GPIO12 PC_BEEP PHONE CD_L CD_GND CD_R MIC LINE_IN_L LINE_IN_R AVDD[2:1] AVSS[2:1] VREF 64 65 66 67 68 69 70 71 83, 72 82, 73 74 I/O I I I I I I I I I I O ESS Technology, Inc. SAM0368-030601 5 ES1988 PRODUCT BRIEF Table 1 Names ES1988 Pin Descriptions (Continued) Pin Numbers 76:75 78:77 79 80 81 I/O O O O O O I 84 I/O O 85 I/O Descriptions Anti-aliasing filter cap for the ADC channel. ADC and DAC reference caps. Line left channel output. Line right channel output. Mono output. MIDI receive data input. Enable MIDI I/O (MPU-401 I/O) by setting PCI 40h [3] = 1. General-purpose input/output. MIDI transmit data output. Enable MIDI I/O (MPU-401 I/O) by setting PCI 40h [3] = 1. General-purpose input/output. If a pull down resistor is used on this pin, then pin 2 is enabled for multifunctionality (IDSEL, RO#, SPDIFO, and PCREQ#). Otherwise, pin 2 may only be used for IDSEL. 86 87 88 91 92 I O I I O PCI reset input. Interrupt request output. PCI bus clock input. Bus master grant input. Bus master request output. AFILT[2:1] CAP[2:1] LINE_OUT_L LINE_OUT_R MONO_OUT RXD GPIO1 TXD GPIO2 (note) RST# INT# PCICLK GNT# REQ# ORDERING INFORMATION Part Number ES1988S Description PCI Audio-Modem Accelerator Package 100-pin LQFP ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898 6 No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. (P) U.S. patents pending. Allego is a registered trademark of ESS Technology, Inc. All other trademarks are owned by their respective holders and are used for identification purposes only. (c) 2001 ESS Technology, Inc. All rights reserved. SAM0368-030601 |
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